The invention relates to a liquid crystal display panel, and in particular to a liquid crystal display panel with a test circuit.
FIG. 1 is a schematic diagram of a display array of a conventional liquid crystal display (LCD) panel. As shown in FIG. 1, a display array 1, formed by interlacing data lines D1 to Dm and scan lines G1 to Gn, is configured on a glass substrate and Each interlaced data line and scan line corresponds to one display unit, for example, interlaced data line D1 and scan line S1 correspond to display unit 100. As with any other display unit, the equivalent circuit of the display unit 100 comprises a switch transistor TFT, a storage capacitor Cs, and a liquid crystal capacitor Clc. A gate of the switch transistor is coupled to the scan line G1, and a drain thereof is coupled to the data line D1, and a source thereof is coupled to a pixel electrode PE.
After the display array of the LCD panel having the above-described configuration is formed, the glass substrate is tested to detect shorts and breaks in the data lines D1 to Dm and the scan lines G1 to Gn. To complete these tests, a liquid crystal display (LCD) device for testing signal line disclosed in U.S. Pat. No. 6,566,902 B2, as shown in FIG. 2, comprises a plurality of data lines DL, an odd-numbered detecting line ODDL, and an even-numbered detecting line EDDL. The odd-numbered detecting line ODDL is commonly connected to odd-numbered data lines DL through data pads 2, and the even-numbered detecting line EDDL is commonly connected to even-numbered data lines DL through data pads 2. The LCD device provides two common electrode lines CLa and CLb arranged on the LCD device to cross each data line DL. The LCD also provides a plurality of electrostatic discharge (ESD) protection circuits 12, each connected between an odd-numbered data line and the common electrode line CLa and between an even-numbered data line and the common electrode line CLb. The LCD device further provides at least two auxiliary ESD protection circuits 14 connected in series between the two separated common electrode lines CLa and CLb. In this LCD device, one common voltage source Vcom provides voltage to both common electrode lines CLa and CLb. In a test process, test signals are applied to the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL and then to the odd-numbered data lines and the even-numbered data lines, respectively, to thereby detect faults of the data lines DL, such as a short between two adjacent data lines DL. Similarly, the same test configuration is employed in the scan lines.
In the related art, the data lines DL are connected to the common electrode lines CLa or CLb through ESD protection circuits 12, which are further connected to the same common voltage source Vcom through auxiliary ESD protection circuits 14. Thus, the test signals on the odd-numbered detecting line ODDL and the even-numbered detecting line EDDL interfere with each other in a test process, resulting in an inaccurate test of signal lines.